1. Field of the Invention
This invention relates to semiconductor memory cells, and in particular to cells suitable for use in content addressable memories in which a memory is searchable by the contents of the memory data.
2. Description of Related Art
U.S. Pat. No. 4,890,260 discloses a configuration using a content addressable memory (CAM). Referring to FIG. 1 which illustrates this configuration, the CAM cell array 11 is connected to a bit line descriptor circuit 1. Bit line descriptor circuit 1 includes a programmable bit line writing circuit, a comparand register, a mask register, and a sense amplifier (all not shown). The comparand register programs the programmable bit line writing circuit with the data to be written onto the bit lines BL and BL coupled to CAM cell array 11. Data is read from CAM cell array 11 through bit lines BL and BL with a predetermined word line WL selected. The signal on bit lines BL and BL is amplified by the sense amplifier.
Data in the mask register is used for programmable bit masking. A logic "1" in the mask register will overwrite the data in the comparand register, whereas a logic "0" in the mask register will allow the corresponding data in the comparand register to appear on the bit line for writing in a cell. Any or all bits can be masked in this manner.
Descriptor circuit 1 exchanges data with bit bus 10. A row decoder 2 is connected to CAM cell array 11 by a plurality of word lines WL for selecting different words in the array. A bit line precharge circuit 3, which precharges the bit lines to the optimal levels for high speed cell reading, is connected to CAM cell array 11 through a plurality of bit lines BL' and BL'. CAM cell array 11 is connected to a word masking and reset circuit 4, match detector 5, and priority encoder 6 via a plurality of match lines ML.
Word masking and reset circuit 4 masks any or all words with an empty or skip bit. The entire array is reset by resetting all the empty bits. Both of these operations are well-known in the art and, therefore, are not explained in further detail. Match detector 5 detects a "no match" or "match" condition. Priority encoder 6 encodes the address of the location in CAM cell array 11 when a "match" condition occurs.
The control logic 7 provides inputs to word masking and reset circuit 4, match detector 5, and priority encodes 6 in response to instructions received from bus 10. Specifically, instructions received from bus 10 generate the appropriate internal timings to accomplish the operations of each circuit.
A typical content addressable memory cell, shown in FIG. 2, comprises nine transistors. Transistors 206-209 form a memory cell 216. Information is stored in the form of voltage levels in memory cell 216. Memory cell 216 has two states: logic state "0" and logic state "1". For example, if logic state "0" is designated by node 204 having a high voltage and node 205 having a low voltage, then logic state "1" has the opposite stored voltages, i.e. node 204 having a low voltage and node 205 having a high voltage.
In logic state "0" the high voltage on node 204 turns on N-channel transistor 209 and turns off P-channel transistor 207. The low voltage applied to node 205 turns on P-channel transistor 206 and turns off N-channel transistor 208. The voltage on node 204 remains high because current flows through transistor 206 from voltage source Vdd, which is typically 5 volts. The voltage on node 205 remains low because current flows through transistor 209 to voltage source Vss (typically ground).
In logic state "1" the transistors which were on in the logic "1" state are now off, and the transistors which were off are now on, thereby providing a low voltage on node 204 and a high voltage on node 205. Node 204 remains low as current flows through transistor 208 to voltage source Vss (ground), while node 205 now remains high as current flows from voltage source Vdd through transistor 207. Thus, both logic states are stable with neither branch 216A, including transistors 206 and 208, nor branch 216B, including transistors 207 and 209, conducting.
To read memory cell 216, bit lines 200 and 201 are precharged to a high voltage. Transistors 202 and 203 are subsequently turned on by a high voltage on word line 215. The logic state stored by memory cell 216 pulls one bit line, 200 or 201, low. For example, if memory cell 216 is in logic state "1" with a low voltage on node 204 and a high voltage on node 205, then bit line complement 200 is discharged through transistors 202 and 208 to ground. Bit line 201 remains charged. The difference in voltage between bit lines 200 and 201 is then sensed.
To write a logic state in the memory cell 216, data is placed on bit line 200 and data complement ("data") is placed on bit line complement 201. Applying a high voltage to word line 215 turns on transistors 202 and 203, thereby transferring data and data to nodes 204 and 205, respectively. This voltage transfer drives memory cell 216 into the desired configuration.
During a comparison operation, data is placed on bit line 201 and data is placed on bit line complement 200. For example, assume memory cell 216 stores a logic "0". A match fail condition results when a low voltage and a high voltage are provided on bit lines 200 and 201, respectively, in the comparison mode. To ensure transistors 202 and 203 remain off, the voltage on word line 215 remains low. The high voltage stored on node 204 is applied to the gate of N-channel pass transistor 211, thereby turning on pass transistor 211. The low voltage on node 205 is applied to N-channel pass transistor 210. Therefore, pass transistor 210 remains off. Thus, with transistor 211 on, data (i.e. a high voltage) on bit line 201 is applied to the gate of N-channel transistor 213, thereby turning on this transistor as well. Because transistor 213 turns on, current flows through transistor 213 to voltage source Vss (ground), thereby discharging the voltage on match line 214 which was precharged for the comparison operation. Thus, in summary, if the data match those in memory cell 216, then match line 214 remains charged. If memory cell has data that do not match, match transistor 213 turns on and discharges match line 214.
A drawback of the above-described content addressable memory is that the bit lines must be discharged to zero to prepare for a comparison operation. Therefore, a need arises for an improved content addressable memory.
Another drawback is the large number of transistors required, nine in this configuration, which introduces an undesirable increase in the size of the array. Therefore, a need also arises for a smaller content addressable memory.